1. Field of the Invention
This invention relates to a semiconductor memory device capable of storing binary or more-valued data in, for example, a single memory.
2. Description of the Related Art
In a NAND flash memory, all of or half of a plurality of memory cells arranged in the row direction are connected via bit lines to corresponding latch circuits, respectively. Each latch circuit holds data in writing or reading data. Data is written or read all at once into or from all of or half of the cells arranged in the row direction (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 2004-192789).
In addition, data is erased in, for example, blocks. The threshold voltage of a memory cell is made negative in an erase operation and electrons are injected into the memory cell in a write operation, thereby making the threshold voltage positive. However, since the memory cells are connected in series in a NAND flash memory, the unselected cells have to be in the on state in a read operation. For this reason, a higher voltage (Vread) than the threshold voltage is applied to the gates of the unselected cells. Therefore, the threshold voltage in a write operation must not exceed Vread. In a write sequence, the threshold voltage distribution has to be suppressed so as not to exceed Vread by carrying out a program operation and a program verify read operation. This causes a problem: the speed of the program becomes slower.
To store a large amount of data, a multivalued memory which stores two or more bits in a single cell has been developed. In the multivalued memory, for example, to store two bits in a single cell, four threshold voltages must be set. For this reason, the distribution of one threshold voltage has to be made narrower than in a memory which stores one bit in one cell. In this control, too, a program operation and a program verify operation must be repeated as described above, which causes a problem: the write speed becomes slower.
Moreover, to store 3-bit data or 4-bit data into one cell, 8 or 16 threshold voltages have to be set. For this reason, the threshold width of one threshold voltage must be made very narrow.
To solve this problem, it is conceivable that a threshold voltage is set as data to a negative threshold voltage. In such a configuration, since the number of positive threshold voltages to be set can be decreased in the range of Vread, the distribution width of one threshold voltage can be made wider, enabling high-speed writing. However, when a negative voltage is applied to the gate of the memory cell, a negative potential has to be supplied to a word line. For this reason, a high withstand voltage transistor (H. V. Tr) constituting a row decoder has to be formed in a p-well structure and a negative voltage has to be applied to the well. This causes a problem: the manufacturing process becomes complicated.
To overcome this problem, an external power supply or an internal power supply supplies a bias voltage to the source of the cell and the well in a read and a verify operation, thereby making the potentials of the source and well higher than the potential of the word line. This seemingly produces a situation equivalent to a case where a negative voltage is applied to the word line, thereby reading a negative threshold value. This technique has been proposed (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 3-283200). However, this technique has been applied to the test mode of memory cells, and not to the normal operation mode. In addition, when the internal power supply circuit applies a bias voltage to the source and well, large currents flow from a large number (16 k to 32 k) of bit lines into the internal power supply circuit, which causes a problem: the internal power supply circuit is unstable. Therefore, a semiconductor memory device capable of setting a negative threshold voltage in a memory cell and operating stably has been desired.